| Function | Description | | :--- | :--- | | | Manages requests from multiple bus masters (devices wanting to initiate transfers). Grants access based on a fairness algorithm (e.g., rotating priority). | | Address Decoding | Determines whether a memory or I/O access from the CPU targets a PCI device or main memory. Routes accordingly. | | Data Transfer Control | Orchestrates burst transfers, target termination, and error handling (parity checking, master abort, target abort). | | Configuration Access | Implements Configuration Space (256 bytes per device) for resource assignment (Base Address Registers – BARs), interrupt routing, and device identification. | | Bridge Logic | Connects primary (CPU side) to secondary (PCI bus side) interfaces. Handles transaction forwarding, buffering, and speed adaptation. | 4. System Topology & PCI Hierarchy A typical PCI system uses a host bridge (the PCI Controller) to connect the CPU/memory to PCI bus 0. Additional PCI-to-PCI bridges allow expansion.
The hardware decodes CONFIG_ADDRESS and routes the subsequent read/write to the correct device. 10. Common Issues & Debugging | Issue | Likely Cause | PCI Controller Role | | :--- | :--- | :--- | | Device not detected | BAR assignment failed or decoding disabled | Controller does not forward cycles to device. | | DMA data corruption | Incorrect bus mastering setup or no snooping | Controller failed to arbitrate or bridge coherency. | | PCI parity error | Signal integrity or misconfigured device | Controller reports via status register and may assert PERR#. | | Target abort | Device didn't respond within DEVSEL timing | Controller returns all-ones data and sets Received Target Abort bit. | pci controller
| Feature | Legacy PCI Controller | PCIe Root Complex | | :--- | :--- | :--- | | Topology | Shared parallel bus | Point-to-point serial lanes (x1, x4, x8, x16) | | Bandwidth (per lane) | 133 MB/s (max) | 2 GB/s per direction (PCIe 6.0) | | Configuration Space | Same 256-byte header | Extended to 4KB (PCIe capability structures) | | Enumeration | Type 0/1 cycles | Same, but forwarded as Transaction Layer Packets (TLPs) | | Interrupts | Legacy INTx lines | MSI/MSI-X (Message Signaled Interrupts) | | Function | Description | | :--- |
PCIe Root Complexes still expose PCI-compatible configuration mechanisms. Operating systems use the same driver model for PCI and PCIe devices. 9. Practical Example: Programming a PCI Controller To access a PCI device’s configuration space on x86: Routes accordingly
